Thermal Ground Plane for Chip-Level Electronics Cooling


The three-dimensional thermal ground plane was developed in response to the needs of high-power density electronics applications in which heat must be removed as close to the chip surface as possible. The novel design for this planar cooling device was proposed with three key innovations in the evaporator, wick, and reservoir layer, which provided enhanced and reliable cooling performance without wick dryout and back flows. For the evaporator and reservoir layer, a combination of a tapered channel and a triple-spike microstructure was designed to break up the pinned meniscus at the end of the vapor and liquid channels. The overall microstructure had three spikes where the main liquid meniscus was separated by a middle spike and then continued to flow between the tapered walls of the middle and side spikes. For the wick layer, a nanowire-integrated microporous silicon membrane was developed to overcome dryout by driving the coolant out of the channels and spreading the coolant on top of the wick surface with the assistance of extended capillary action. This innovative design used nanowires to extend and enhance capillary force, especially at the end of the pores where the coolant was pinned and unable to overflow out of the pores. The chronic dryout problem in micro cooling devices could be solved by these innovative designs.

To analyze the thermal-fluid system, fluid dynamic and phase-change models were used to calculate thermodynamic and fluidic properties, such as operating temperature, pressure, vapor-liquid interface radius of curvature, and rate of bubble formation. The microscale heat conduction theory derived from traditional Fouriers law with classical size effect and effective medium theory were used to calculate the thermal conductivities of nanowires and porous silicon wick in the cross-plane direction, respectively. The theoretical results of porous silicon showed good agreement with the experimental results measured by the 3ω technique, demonstrating the reduction of thermal conductivity from bulk silicon. Cooling performance of the developed device was demonstrated experimentally with a micro ceramic heater, thermocouple modules, and microfabrication techniques, including photoelectrochemical etching to create porous silicon, deep reactive-ion etching to form a thin wick membrane, and hydrothermal synthesis to grow nanowires on top of the wick membrane. This study shows the feasibility of reliable, continuous, and high-performance micro cooling devices using enhanced capillary forces to address the increasing requirements of thermal management for chip-level electronics.

Publication date: 
December 31, 2014
Publication type: 
Ph.D. Dissertation
So, H. (2014). Thermal Ground Plane for Chip-Level Electronics Cooling. United States: University of California, Berkeley.

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