In this work the issues involved in designing pipeline Analog to Digital Converters in fine line technologies are discussed. In particular, we focus on the design of the interstage amplifier within the pipeline. We compare open loop voltage and current mode approaches to amplifier design and suggest solutions to common current mode design problems. Further, we propose architectural modifications to the pipeline enabling relaxed amplifier specifications.
May 31, 2006
Katsis, D. (2006). Design of Moderate Resolution High Speed Pipeline ADCs in Fine Line Technologies: Research Project. United States: University of California, Berkeley.