Design and Implementation of Sigma-Delta Force-Balance Microaccelerometers


The first goal of this research is to investigate the issues involved in the design of a sigma-delta force- balance surface-micromachined accelerometer. The second goal is to successfully design, fabricate, and test a monolithic microaccelerometer.

Various design issues have been addressed. Quantization, brownian, electronic, sense-force, and clock-jitter noise have been analyzed. System stability has been studied. Two different sensing schemes have been presented. They are the bootstrap technique and the charge-transfer technique. Issues such as noise, bandwidth, and nonlinearity for each approach have been analyzed. The design of the comparator and the DAC have been discussed. Trade-offs of a vertical-sense design versus a lateral-sense design have been examined.

A vertical-sense monolithic sigma-delta microaccelerometer have been designed. The design employs the charge-transfer technique for sensing. It utilizes correlated double sampling for offset and flicker noise cancellation. Comb fingers have been used to provide levitation force. Access to several internal bias nodes are provided. FEM simulations have been done to determine the frequency of the fundamental mode and the higher modes. The design is fabricated in a 3um BiCMOS single- structural layer technology. Details of the design is documented in chapter 3. A test board has been built to provide a clock signal and supplies to the accelerometer.

A test setup with a shaker table as the excitation source has been assembled for testing. The accelerometer has been shown to achieve a 50dB dynamic range measured in a 50Hz bandwidth with a +/-5g input range is described. The converter operates at 500kNz, exhibits a noise floor of 1.6mg/Hz.

Publication date: 
October 31, 1994
Publication type: 
Master's Thesis
Lu, C. Y. (1995). Design and Implementation of Sigma-delta Force-balance Microaccelerometers. United States: University of California, Berkeley.

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