Fabrication of Exposed Gate Field Effect Transistors for Sensor Applications


A dual dielectric structure was used as the gate insulating layer of an exposed gate field effect transistor in sensor applications. This structure, which consisted of thermally grown silicon dioxide and chemical vapor deposited (CVD) silicon nitride, provided elecmcal stability and physical durability. Conditions to reproducibly fabricate a combined silicon dioxide/silicon nitride gate insulator with a total thickness less than 15nm (4.5 nm oxide/8.5 nm nimde) and a fixed insulator charge on the order of 1x10^11/cm2 were determined. A metal, insulator, semiconductor (MIS) structure with aluminum electrode incorporating the dual dielectric displayed flat band voltage shifts (instabilities) after heating to 400C. Results indicated that the instability was due to aluminum diffusion into the nimde layer. MIS structures with heavily doped polycrystalline silicon (polysilicon) electrodes did not display this instability.

A complete process flow for the fabrication of field effect pansistors which incorporated the oxide/nitride dielecmc and exposed the polysilicon layer was developed. These devices were suitable for subsequent gate modification and use as chemical sensors in aqueous solution. A novel device geometry which enhanced device sensitivity and stability was developed.

Exposed gate field effect transistors with silicon dioxide only gate insulators were used for a novel sensing application. These devices were used as an in-situ monitor of the effects of downstream oxygen plasma processing on the charge characteristics of the silicon/silicon dioxide system. The source to drain current of an exposed gate field effect transistor was monitored before, during, and after plasma processing. The in-situ approach was successful and non-invasive. Devices displayed a drain current decrease, at a fived source to drain potential difference, during plasma exposure indicating an increase in the fixed negative charge in the oxide and/or a decreased transconductance due to an increase in the density of interface traps. A portion of the drain current decrease was recoverable after exposure to room air or in-situ exposure to water vapor and was most likely caused by electron trapping at water related uaps in the oxide. The remainder of the drain current decrease was recovered after annealing at 400C in forming gas and was most likely caused by electron trapping at neutral electron traps and/or an increase in non-water related interface rrap density. Substrate currents were generated during plasma exposure and electron injection from the substrate was the probable source of electrons trapped in the oxide. Exposure upstream of the plasma and with LiF, quartz, pyrex and silicon shields indicated that vacuum ultraviolet (VUV) photons with energies greater than the bandgap of SiQ (9eV) are partially responsible for the non-recoverable drain current decrease. Exposure downstream of the plasma but in a non-line of sight position indicated that non- recoverable drain current decreases were also caused without exposure to VUV photons. Downstream exposure with a grounded screen between the device and the discharge indicated that electron injection due to surface charging was responsible for these effects.

Albert William Flounders
Dennis W. Hess
Publication date: 
May 31, 1992
Publication type: 
Ph.D. Dissertation
Flounders, A. W. (1992). Fabrication of Exposed Gate Field Effect Transistors for Sensor Applications. United States: University of California, Berkeley.

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