To meet demands for mobile electronic, power has become limiting factor for most ADC design. In pipelined ADC structure, Inter-stage Gain circuits are the most power hungry building block. Conventionally, Inter-stage gain circuits are implemented using feedback an OTA with a less-than-1 feedback factor (i.e. 1/2 to 1/3). This approach is costly because these OTAs drive not only the load capacitors, but also the sampling and feedback capacitors. As a result, the power consumption of these amplifiers is a feedback factor (i.e., 2 to 3X) worse than their counterparts in unity gain feedback configuration. The current state-of-art pipelined ADC has a FOM of 100fJ per conversion step [1]. In this project, we use “passive amplifiers†to implement inter-stage gain block, thus, eliminating this “feedback factor†penalty. The target performance of this prototype is 11b 200Ms/s with a power consumption less than 20mW (equivalently, 50 fJ per conversion step) using TSMC 90nm CMOS process. [1] Boulemnakher, M. Andre, E. Roux, J. Paillardet, F. "A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS", ISSCC, 2008.
Project end date: 08/12/10