The electron in Paul trap system has been recently proposed as a candidate for qubits in quantum information processing. In such a system, floating electrons are confined in vacuum using oscillating electric fields. Feasibility studies and experimental trapping at room temperature have shown that electrons satisfy all DiVincenzo's criteria, a common standard used to determine whether a system can be a good candidate to perform quantum computation. More importantly, electrons have several advantages in quantum information processing as compared to trapped ions. Electrons are spin-½ particles, which are intrinsic two-level systems with no information leakage during processing. Since electrons are controlled by microwave pulses and magnetic field gradients, they do not require optical access to the system to drive transitions, which is beneficial for scalability. In addition, the lighter mass of electrons enables larger trap frequencies and hence faster gate operation time. Lastly, electrons can potentially be co-trapped with ions due to their particle nature, and also interact electronically with superconducting circuits, which opens up possibilities for hybrid quantum architectures. In order to achieve long electron lifetimes, high readout and gate fidelity, the trapped electron system needs to operate in cryogenic temperatures around 0.4K, but the stable operation and readout of such a system have yet to be demonstrated. Currently, the microwave control and readout of trapped electron systems in cryogenic environments remain challenging, and it is critical to develop high-performance and low-power cryogenic circuits to demonstrate the feasibility of the system.
In this work, we propose using cryogenic CMOS processes to design and fabricate miniaturized electron traps, with the potential to integrate the trap directly with CMOS circuits for readout and control to reduce parasitic losses, improve interface losses, and facilitate future scaling. Since the electron traps require a 3D geometry, we further propose using the flip-chip technology to bond multiple CMOS chips to form a 3D electron trap with cryogenic compatibility. Such a miniaturized trap enables the system to be operated at higher frequencies and enhances the coupling between electrons to readout circuits, which serves as a good platform for scalable control and high-fidelity readout of trapped electrons.
Project is currently funded by: Federal